Semiconductor wet etchant and method of forming interconnection structure using the same

ABSTRACT

A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH 4   + ) and a chlorine ion (Cl − ).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation application of application Ser. No.12/168,952, filed on Jul. 8, 2008, which claims of priority to KoreanPatent Application Serial No. 10-2007-0068569, filed Jul. 9, 2007, thedisclosure of which is hereby incorporated herein by reference.

SUMMARY

Wet etchant solutions are utilized in the fabrication of semiconductordevices, such as in the formation of interconnection structures ofsemiconductor devices. For example, the fabrication of semiconductordevices typically includes a process in which an insulating layer and aconductive layer are formed on a semiconductor substrate, and then theselayers are subjected to an etching process utilizing an etchantsolution. In contrast to dry etchants, wet etchants are generallycharacterized by radiate etching capability over an entire surface ofthe semiconductor substrate.

Examples of the use of a protecting liquid and an etching liquid in adamascene process are disclosed in U.S. Pat. No. 6,683,007, issued inthe name of Shinya Yamasaki et al.

In one non-limiting aspect of the present invention, a semiconductor wetetchant is provided which includes deionized water, and a fluorine-basedcompound, an oxidizer and an inorganic salt mixed in the deionizedwater. A concentration of the fluorine-based compound is 0.25 to 10.0 wt% based on a total weight of the etchant, a concentration of theoxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, anda concentration of the inorganic salt is 1.0 to 5.0 wt % based on atotal weight of the etchant. The inorganic salt includes at least one ofan ammonium ion (NH₄ ⁺) and a chlorine ion (Cl⁻).

In another non-limiting aspect of the present invention, a method offorming an interconnection structure is provided, which includesproviding a semiconductor substrate having opposite main and backsurfaces, and a side surface extending between the main surface to theback surface, forming a first insulating layer on the semiconductorsubstrate, wherein the first insulating layer is located over the main,back and side surfaces of the semiconductor substrate, and forming asecond insulating over the first insulating layer, wherein the secondinsulating layer is located over the main and side surfaces of thesemiconductor substrate. The method further includes sequentiallyforming first and second metal layers over second insulating layer,where the first metal layer is located over the main and side surfacesof the semiconductor substrate, and the second metal layer is locatedover the main surface of the semiconductor substrate, and performing asemiconductor wet etching process on the first metal layer and the firstand second insulating layers. The semiconductor wet etching process isperformed using a semiconductor wet etchant including a mixture ofdeionized water, a fluorine-based compound, an oxidizer and an inorganicsalt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt% based on a total weight of the etchant, a concentration of theoxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, anda concentration of the inorganic salt is 1.0 to 5.0 wt % based on atotal weight of the etchant. The inorganic salt comprises at least oneof an ammonium ion (NH₄ ⁺) and a chlorine ion (Cl⁻).

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of the presentinvention will become more apparent from the detailed description thatfollows, with reference to the accompanying drawings. The drawings arenot necessarily to scale, with emphasis instead being placed uponillustrating principles of embodiments of the present invention.

FIG. 1 is a flowchart of a semiconductor damascene process according toan embodiment of the present invention.

FIG. 2 is a plan view of a semiconductor substrate which may be utilizedin the process of FIG. 1 according to an embodiment of the presentinvention.

FIG. 3 is a cross-sectional view showing a first interconnection formingstructure taken along line I-I′ of FIG. 2 after a semiconductordamascene process of FIG. 1 is partially performed.

FIG. 4 is a cross-sectional view showing a second interconnectionforming structure taken along line I-I′ of FIG. 2 after a semiconductordamascene process of FIG. 1 is partially performed.

FIGS. 5 and 6 are a plan view and a cross-sectional view, respectively,for use in describing a method of applying a semiconductor wet etchantto the first and second interconnection forming structures of FIGS. 3and 4.

FIG. 7 is a cross-sectional view showing the first interconnectionstructure after applying a semiconductor wet etchant to the firstinterconnection forming structure of FIG. 3.

FIG. 8 is a cross-sectional view showing the second interconnectionstructure after applying a semiconductor wet etchant to the secondinterconnection forming structure of FIG. 4.

FIGS. 9 to 11 are graphs for use in describing a method of forming asemiconductor wet etchant according to embodiments of the presentinvention.

DETAILED DESCRIPTION OF EMBODIMENT

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. This invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. Althoughthe terms “selected,” “different”, “predetermined”, “part” and “therest” may be used to denote several elements herein, it may beunderstood that the elements are not limited to these terms. These termsonly used to distinguish one element from another element. For example,without departing from a scope of the invention, a first metal layer maybe named to a second metal layer, and the second metal layer may benamed to the first metal layer. Here, as used herein, a term “and/or”includes all combinations which can be inferred from listed items havingat least one relationship. Particularly relative terms such as “outer,upper, more, gradually and on” may be used to make a simple descriptionfor a relative relationship between other element and one figure or afigure illustrated in the drawings. Moreover, technical terms usedherein are not used to define the invention but to simply describespecific aspects.

A semiconductor wet etchant and a method of forming an interconnectionstructure using the same according to embodiments of the presentinvention will now be described in detail with reference to accompanyingdrawings.

FIG. 1 is a flowchart of a semiconductor damascene process according toan embodiment of the present invention, and FIG. 2 is a plan viewshowing a semiconductor substrate which may be utilized in the processof FIG. 1.

In step S10 of FIG. 1, at least one semiconductor substrate 100 is beprepared as shown by way of example in FIG. 2. The semiconductorsubstrate 100 of this example includes a main surface, a back surfaceand a side surface. The main and back surfaces of the semiconductorsubstrate 100 are disposed parallel and opposite to each other, and theside surface of the semiconductor substrate 100 extends between the mainand back surfaces of the semiconductor substrate 100.

The main surface of the semiconductor substrate 100 of this exampleincludes a device-forming region 106 and a device-excluding region 109which surrounds the device-forming region 106. The device forming region106 and the device excluding region 109 contact each other in thisexample with a region-dividing line 103 defined therebetween. In FIG. 2,the device-forming region 106 is shown as having a predetermineddiameter D, and the device-excluding region 109 is shown as having awidth W1.

FIG. 3 is a cross-sectional view showing a first interconnection formingstructure taken along line I-I′ of FIG. 2 after a semiconductordamascene process of FIG. 1 is partially performed. FIG. 4 is across-sectional view showing a second interconnection forming structuretaken along line I-I′ of FIG. 2 after the semiconductor damasceneprocess of FIG. 1 is further partially performed.

Referring collectively to FIGS. 1, 3 and 4, in step S20 of FIG. 1, firstand second insulating layers 110 and 120 are sequentially formed on thesemiconductor substrate 100. The first and second insulating layers 110and 120 may, for example, be a silicon nitride layer and a silicon oxidelayer, respectively.

The first insulating layer 110 may be formed on the main, back and sidesurfaces of the semiconductor substrate 100. To this end, the firstinsulating layer 110 may be formed using a semiconductor diffusion tube.

The second insulating layer 120 may be formed on the main and sidesurfaces of the semiconductor substrate 100 to cover the firstinsulating layer 110. To this end, the second insulating layer 120 maybe formed by a plasma enhanced chemical vapor deposition (PECVD)technique.

As mentioned above, the first insulating layer 110 may be formed of asilicon nitride layer, and the second insulating layer 120 may be formedof silicon oxide. However, the embodiment is not limited in thisrespect. As other examples, the first insulating layer 110 may be formedof at least one stack of a silicon oxide layer and a silicon nitridelayer, where the silicon nitride layer constitutes an uppermost portionof the first insulating layer 110, and the second insulating layer 120may be formed of a silicon oxide layer and a silicon nitride layer,which are sequentially stacked by a semiconductor diffusion tube, aPECVD technique or a combination thereof. In this example, the siliconoxide layer in the first insulating layer 110 may have a dielectriccoefficient ranging from 3.0 to 4.5, and the silicon oxide layer in thesecond insulating layer 120 may have a dielectric coefficient rangingfrom 2.0 to 3.0.

In step S30 of FIG. 1, at least one trench 130 is formed in the firstand second insulating layers 110 and 120, as shown in FIGS. 3 and 4. Thetrench 130 may be formed to expose the semiconductor substrate 110through the first and second insulating layers 110 and 120 while thesemiconductor damascene process is being performed. The trench 130 ofthis example is disposed in the device-forming region 106 (FIG. 2). Thetrench 130 may instead be disposed in the device-excluding region 109(FIG. 2).

In step S40 of FIG. 1, a first metal layer 140 is formed on the secondinsulating layer 120 to conformally cover the trench 130 as shown inFIGS. 3 and 4. The first metal layer 140 may be disposed on the main andside surfaces of the semiconductor substrate 100. As an example, thefirst metal layer 140 is formed of a diffusion barrier layer and acopper seed layer, which are sequentially stacked. The diffusion barrierlayer may prevent diffusion of copper atoms in the copper seed layerinto the first and second insulating layers 110 and 120 and thesemiconductor substrate 100. As examples, the diffusion barrier layermay be formed of metal, metal nitride or combinations thereof, such astitanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride(TaN) or a combination thereof.

Referring again to FIGS. 1, 3 and 4, in step S40 of FIG. 1, a secondmetal layer 150 is formed on the first metal layer 140 to fill thetrench 130 as shown in FIGS. 3 and 4. The second metal layer 150 may,for example, be formed by an electroplating technique, and may, forexample, be formed of copper or a combination material including thecopper. In this example, the second metal layer 150 is formed only onthe main surface of the semiconductor substrate 100, or morespecifically, only on the device-forming region 106 (FIG. 2) of thesubstrate 100.

Formation of the second metal layer 150 may result in the formation ofsecond metal layer residues 155 due to characteristics of theelectroplating process. Such second metal layer residues 155 may beformed in the peripheral region of the main surface of the semiconductorsubstrate 100, and on the side and back surfaces of the semiconductorsubstrate 100 as shown in FIGS. 3 and 4.

Referring to FIG. 3, in step S50 of FIG. 1, a mask pattern 170 is formedon the first and second metal layers 140 and 150. In this example, themask pattern 170 to cover the second metal layer 150 and an adjacentportion of the first metal layer 140, which exposing the second metallayer residues 155. Accordingly, the structure illustrated in FIG. 3constitutes an interconnection forming structure 184.

The interconnection forming structure 188 of FIG. 4 differs from that ofFIG. 3 in that a third insulating layer 160 is formed on the first andsecond metal layers 140 and 150, and prior to formation of the maskpattern 170. The third insulating layer 160 may, for example, be asilicon oxide layer or a silicon nitride layer. As another example, thethird insulating layer 160 may be formed of at least one stack of asilicon oxide layer and a silicon nitride layer. Here, the thirdinsulating layer 160 may be formed by a semiconductor diffusion tube, aPECVD technique or a combination thereof. The silicon oxide layer in thethird insulating layer 160 may have a dielectric coefficient rangingfrom 2.0 to 3.0.

The mask pattern 170 may, for example, be formed of photoresist or polysilicon. The mask pattern 170 may be formed to be spaced a predeterminedwidth W2 from the side surface of the semiconductor substrate 100, andmay partially overlap the device-excluding region 109 of FIG. 2 (i.e.,W2 may be less than W1).

A method of forming a semiconductor wet etchant (steps S60, S70 and S80)according to embodiments of the present invention will now be describedwith reference to the graphs of FIGS. 9 to 11. The semiconductor wetetchant is a solution which may reduce a copper concentration in thesemiconductor substrate when etching the first interconnection formingstructure 184 of FIG. 3 or the second interconnection forming structure188 of FIG. 4.

Referring to FIGS. 1 and 9, in step S60 of FIG. 1, deionized water andchemical materials were prepared in order to form a semiconductor wetetchant. The chemical materials may include a fluorine-based compound,an oxidizer, an inorganic salt and a surfactant. Several kinds ofsolutions were prepared by mixing the chemical materials with thedeionized water. In order to test the solutions, several firstinterconnection forming structures 184 as shown in FIG. 3 were prepared.

The respective solutions were applied to the first respectiveinterconnection forming structures 184 rotating at 1500 rpm/60 (sec.)for 10 to 120 seconds in a single-type semiconductor wet etchingapparatus. Here, the respective first interconnection forming structures184 may be disposed on a substrate chuck of the single-typesemiconductor wet etching equipment and rotated together with thesubstrate chuck thereof. Subsequently, the respective firstinterconnection forming structures 184 were rinsed with the deionizedwater while rotating at 1500 rpm/25 (sec.) in the single-typesemiconductor wet etching equipment, and then dried with nitrogen gaswhile rotating at 2500 rpm/30 (sec.). Here, the respective solutionswere applied only to the side and back surfaces of the respective firstinterconnection forming structures 184. The main surface of therespective first interconnection forming structure 184 was surrounded bya protection layer during the application of the respective solutions.

The protection layer may be formed, for example, of an inert gas,nitrogen gas or deionized water. Here, the main, side and back surfacesof the respective first interconnection forming structures 184correspond to the main, side and back surfaces of the semiconductorsubstrate 100. The respective solutions were sequentially applied to thefirst metal layer 140, and the first and second insulating layers 110and 120 until the side and back surfaces of the semiconductor substrate100 of FIG. 3 were exposed. After that, a copper concentration of eachof the first interconnection forming structures 184 was measured by avapor phase decomposition (VPD) induced couple plasma (ICP)-massspectroscopy (MS). Weight percent (wt %) of the chemical materials inthe respective solutions and copper concentrations (atoms/cm²) in therespective first interconnection forming structures 184 corresponding tothe respective solutions are listed in Table 1.

TABLE 1 Solution Fluorine-based Deionized Copper compound OxidizerInorganic salt Surfactant water Concentration Sample (wt %) (wt %) (wt%) (ppm) (wt %) (atoms/cm2) Reference — — — — —  1.0E13 A HF (0.25) — —— DI (99.75) 2.25E12 B HF (10.0) — — — DI (90.00) 2.25E12 C HF (2.5)H₂O₂ (0.45) — — DI (97.05) 1.61E12 D HF (2.5) H₂O₂ (0.45) — 50 DI(97.05) 1.71E11 E HF (2.5) H₂O₂ (3.6) — 50 DI (93.90) 6.52E11 F HF (5.0)H₂O₂ (0.45) — 50 DI (94.55) 4.51E10 G HF (10.0) H₂O₂ (0.45) — 50 DI(89.55) 1.71E10 H HF (10.0) H₂O₂ (3.6) — — DI (86.40) 0.80E10 I HF(10.0) H₂O₂ (3.6) — 50 DI (86.40) 4.81E10 J TMAF (10.0) H₂O₂ (3.6) — —DI (86.40) 1.41E11 K TMAF (10.0) H₂O₂ (3.6) — 50 DI (86.40) 2.42E11 L HF(10.0) HNO₃ (3.6) — — DI (86.40) 0.10E10 M HF (10.0) HNO₃ (3.6) — 50 DI(86.40) 0.24E10 N HF (10.0) H₂O₂ (3.6) NH₄Cl (5.0) — DI (81.40) 0.24E10O HF (10.0) H₂O₂ (3.6) HCl (1.0) — DI (85.40) 0.18E10 P HF (10.0) H₂O₂(3.6) NH₄Cl (5.0) 50 DI (81.40) 0.33E10 Q HF (10.0) H₂O₂ (3.6) HCl (1.0)50 DI (85.40) 0.15E10 R HF (10.0) H₂O₂ (3.6) (NH₄)₂CO₃ (5.0) 50 DI(81.40) 1.01E10 S HF (10.0) H₂O₂ (3.6) NH₄Br (5.0) 50 DI (81.40) 0.51E10

Herein, a reference sample is a first interconnection forming structureto which any solution is not applied.

First, an experimental record of selecting a semiconductor wet etchantfrom among the solutions will be described with reference to Table 1 andFIG. 9. As shown in FIG. 9, samples A and B in Table 1 have lower copperconcentrations than the reference sample. This is because samples A andB do not have a first metal layer 140, and first and second insulatinglayers 110 and 120, which are disposed on side and back surfaces of thesamples A and B.

More specifically, the first metal layer 140, and the first and secondinsulating layers 110 and 120 were removed from the side and backsurfaces of the samples A and B by solutions respectively havinghydrogen fluoride (HF) concentrations of 0.25 and 10.0 wt %. Thus,samples A and B, unlike the reference sample, do not have second metallayer residues 155 on the first metal layer 140. Accordingly, thesamples A and B may have lower copper concentrations than the referencesample. However, copper concentrations were not different betweensamples A and B even though the hydrogen fluoride (HF) concentrations inthe solutions were different from each other, for example, 0.25 and 10.0wt %.

As shown in FIG. 9, the copper concentrations of samples C, D, F and Gare gradually decreased in order, as a hydrogen fluoride (HF)concentration of solutions having the same hydrogen peroxide (H₂O₂)concentration of 0.45 wt % is increased from 2.5 to 10.0 wt %. This isbecause the solutions have the same oxidation degree with respect to thesecond metal layer residues 155 and a high etch rate with respect to thefirst metal layer 140 and the first and second insulating layers 110 and120 on the side and back surfaces of the samples C, D, F and G byincreasing the hydrogen fluoride (HF) concentration.

Since the solutions applied to the samples C, D, F and G have oxidizingpower, they may reduce copper concentrations when compared with thesolutions applied to samples A and B of FIG. 9. Moreover, in FIG. 9, adifference in copper concentration exists between samples C and D amongsolutions which have the same hydrogen fluoride (HF) and hydrogenperoxide (H₂O₂) concentrations, but different surfactant concentrations.The surfactant may, for example, be a non-ionized surfactant which iscomposed of a copolymer of ethylene and propylene. The surfactantprevents re-adsorption of the second metal layer residues 155, whichhave been removed with the first metal layer 140, to the semiconductorsubstrate 100.

Also, as shown in FIG. 9, copper concentrations of samples E, H and Iseem to gradually decrease a little, as the hydrogen fluoride (HF)concentrations of solutions having the same hydrogen peroxide (H₂O₂)concentration of 3.6 wt % increase from 2.5 to 10.0 wt %. The copperconcentrations have no large difference among the samples E, H and Iaccording to whether the respective solutions include a surfactanttherein. The surfactant increases the copper concentrations in orderalong the samples H and I in the solutions having a HF concentration of10.0 wt %.

However, as seen in Table 1 and FIG. 9, solution applied to sample I mayfurther decrease the copper concentrations than the solutions applied tosamples A and B.

A description of the experimental record of selecting the semiconductorwet etchant according to embodiments of the present invention from amongthe solutions will be continued with reference to Table 1 and FIG. 10.

Referring to Table 1 and FIG. 10, in step S60 of FIG. 1, samples A and Bof FIG. 10 are the first interconnection forming structures 184 of FIG.3 which are treated with solutions having hydrogen fluoride (HF)concentrations of 0.25 and 10.0 wt % along Table 1, respectively,similarly to that described in FIG. 9. Also, FIG. 10 shows that samplesH, I, J and K of Table 1 have smaller copper concentrations than thesamples A and B. More particularly, FIG. 10 shows that the copperconcentrations of the samples H, I, J and K are gradually increased asthe solutions have the same hydrogen peroxide (H₂O₂) and fluorine-basedcompound of 3.6 and 10.0 wt %, and have different kinds offluorine-based compounds as shown in Table 1. The solutions includehydrogen fluoride (HF) or tetra-methyl ammonium fluoride (TMAF;(CH₃)₄NF) as a fluorine-based compound.

A solution having tetra-methyl ammonium fluoride (TMAF; (CH₃)₄NF) has agenerally low etch rate with respect to the first metal layer 140, andthe first and second insulating layers 110 and 120 of FIG. 3 incomparison with a solution having hydrogen fluoride (HF). Accordingly,the solution having tetra-methyl ammonium fluoride (TMAF; (CH₃)₄NF) hashigher copper concentrations in samples J and K than the solution havinghydrogen fluoride (HF) in FIG. 10. Surfactants applied to the samples H,I, J and K gradually increase the copper concentration when used withthe solutions having a fluorine-based compound (HF or TMAF)concentration of 10.0 wt %, similarly to FIG. 9. The fluorine-basedcompound may be at least one of ammonium fluoride (NH₄F), ammoniumbifluoride (NH₄HF₂) and tetra-butyl ammonium fluoride (TBMA;(CH₃CH₂CH₂CH₂)₄NF).

As shown in FIG. 10, samples L and M of Table 1 have lower copperconcentrations than samples H, I, J and K. This is because samples L andM are treated with a solution having a HF concentration of 10.0 wt % anda nitric acid (HNO₃) concentration of 3.6 wt %. That is, the solutionhaving hydrogen fluoride (HF) and nitric acid (HNO₃) has a generallyhigh etch rate with respect to the first metal layer 140 and the firstand second insulating layers 110 and 120 of FIG. 3 in comparison with asolution having hydrogen fluoride (HF) and hydrogen peroxide (H₂O₂).Here, surfactant applied to the samples L and M increase the copperconcentrations when used with the solution having a fluorine-basedcompound (HF) concentration of 10.0 wt %, similarly to FIG. 9. Thenitric acid as an oxidizer may, for example, be substituted by at leastone of sulphuric acid (H₂SO₄), ammonium nitrate (NH₄NO₃), ammoniumiodate (NH₄IO₃) and ammonium disulfate ((NH₄)₂S₂O₅).

As seen in Table 1 and FIG. 10, the solutions applied to samples H, I,J, K, L and M may further decrease the copper concentrations than thesolutions applied to the sample A and B.

Finally, the experimental record of selecting the semiconductor wetetchant according to embodiments of the present invention from among thesolutions will be subsequently described with reference to Table 1 andFIG. 11.

Referring to Table 1 and FIG. 11, in step S60 of FIG. 1 according to thepresent invention, samples A and B of FIG. 11, similarly to thatdescribed in FIG. 9, are the first interconnection forming structures184 of FIG. 3 which are treated with the solutions having hydrogenfluoride (HF) concentrations of 0.25 and 10.0 wt %, respectively.Moreover, in Table 1, solutions applied to samples H and I do notinclude an inorganic salt. The solutions applied to the samples H and Iinclude a fluorine-based compound and an oxidizer, wherein sample Ifurther includes a surfactant. Also, samples N, O, P, Q, R and S ofTable 1 were treated with solutions that have 10.0 wt % hydrogenfluoride (HF) and 3.6 wt % hydrogen peroxide (H₂O₂), and different kindsof inorganic salts from one another. Here, samples N and O were treatedwith solutions that do not include a surfactant, and samples P, Q, R andS were treated with solutions that include a surfactant.

The inorganic salts include ammonium chloride (NH₄Cl), hydrochloric acid(HCl), ammonium carbonate ((NH₄)₂CO₃) and ammonium bromide (NH₄Br). Asshown in FIG. 11, the solutions applied to samples N, O, P, Q, R and Shave lower copper concentrations than those applied to samples H and I.More particularly, solutions having inorganic salts such as ammoniumchloride (NH₄Cl) and hydrochloric acid (HCl) have lower copperconcentrations than those having the inorganic salts such as ammoniumcarbonate ((NH₄)₂CO₃) and NH₄Br. This is because the solutions havinginorganic salts such as ammonium chloride (NH₄Cl) and hydrochloric acid(HCl) detach the first metal layer 140 and the second metal layerresidues 155 of FIG. 3 from the first and second insulating layers 110and 120 using hydrogen fluoride (HF), and allow copper atoms in thefirst and second metal layers 140 and 150 to react with chlorine ion(Cl⁻). Solutions having inorganic salt such as ammonium chloride (NH₄Cl)may allow the copper atoms in the first and second metal layers 140 and150 to react with the chlorine ion (Cl⁻) in accordance with thefollowing representative chemical reaction formula.

Formula 1

CuO(Solid)+Cu(NH₃)₄Cl₂(Aqueous)→2Cu(NH₃)₂Cl(Aqueous)  {circle around(1)}, and

4Cu(NH₃)₂Cl(Aqueous)+O₂(Aqueous)+4NH₄Cl(Aqueous)→4Cu(NH₃)₄Cl₂(Aqueous)+6H₂O(Aqueous)  {circlearound (2)}

More specifically, in {circle around (1)} of Formula 1, ‘CuO (solid)’ isreferred to as a copper layer oxidized in the solution by an oxidizer.Further, ‘Cu(NH₃)₄Cl₂ (Aqueous)’ is referred to a copper atom dissolvedin the solution. CuO reacts with Cu(NH₃)₄Cl₂, thereby generatingby-products, ‘2Cu(NH₃)₂Cl’, in the solution. In {circle around (2)} ofFormula 1, ‘4Cu(NH₃)₂Cl’ reacts with oxygen ‘O₂’ of deionized water andan inorganic salt ‘4NH₄Cl’, thereby generating by-products, ‘4Cu(NH₃)₂Cland 6H₂O’ in the solution. ‘4Cu(NH₃)₂Cl and 6H₂O’ may be discharged fromthe semiconductor wet equipment along with the solution.

The solutions having inorganic salts such as (NH₄)₂CO₃ and NH₄Br exhibitfavorable properties in dissolving the copper atoms in the first andsecond metal layers 140 and 150 as compared to the solutions applied tosamples H and I. According to Table 1 and FIG. 11, the solutions appliedto the samples N, O, P, Q, R and S may further reduce copperconcentrations relative to the solutions applied to samples H and I. Theinorganic salt may, for example, be at least one of ammonium ion (NH₄ ⁺)and chlorine ion (Cl⁻). Moreover, the inorganic salt may be one selectedfrom non-metal atoms bonded to the ammonium ion (NH₄ ⁺) and/or oneselected from metal atoms bonded to the chlorine ion (Cl⁻). Here, thenon-metal atoms may include chlorine (Cl), bromine (Br), iodine (I) andcarbonic acid (CO₃), and the metal atoms may include sodium (Na), kalium(K), calcium (Ca) and cesium (Cs).

Consequently, the semiconductor wet etchant of embodiments of thepresent invention may be obtained from solutions having 0.25˜10.0 wt %fluorine-based compound, 0.45˜3.6 wt % oxidizer, and 1.0˜5.0 wt %inorganic salt in deionized water. The semiconductor wet etchant may beapplied to the first interconnection forming structure 184 shown in FIG.3 to obtain a copper concentration of 0.6E10 (atoms/cm²) or less.Further, the surfactant applied to the samples N, O, P, Q, R and S seemto not largely influence on copper concentrations.

In step S70 of FIG. 1, 0.25˜10.0 wt % fluorine-based compound, 0.45˜3.6wt % oxidizer, and 1.0˜5.0 wt % inorganic salt are mixed with thedeionized water to form a solution as the semiconductor wet etchant.Here, a surfactant may be mixed with the deionized water. When thesurfactant is mixed with the deionized water, the surfactant may have atolerance from the amount (50 ppm) shown in Table 1.

After the formation of the solution, in step S80 of FIG. 1,concentrations of the fluorine-based compound, the oxidizer and theinorganic salt in the solution may be measured by various known methods.Here, if the solution does not satisfy the above conditions of thesemiconductor wet etchant, the solution is discarded, and the processgoes back to step S70 of FIG. 1 to again prepare other solution as thesemiconductor wet etchant. On the contrary, if the solution satisfiesthe above conditions of the semiconductor wet etchant, the solution maybe applied to the first interconnection forming structure 184 of FIG. 3or the second interconnection forming structure 188 of FIG. 4.

FIGS. 5 and 6 are a plan view and a cross-sectional view illustrating amethod of applying a semiconductor wet etchant to first and secondinterconnection forming structures of FIGS. 3 and 4, respectively.

Referring to FIGS. 1, and 3 to 6, in step S90 of FIG. 1, thesemiconductor wet etchant is applied to the first interconnectionforming structure 184 of FIG. 3 or the second interconnection formingstructure 188 of FIG. 4. The semiconductor wet etchant is a solution inwhich 0.25 to 10.0 wt % fluorine-based compound, 0.45 to 3.6 wt %oxidizer and 1.0 to 5.0 wt % inorganic salt are mixed with the deionizedwater. The semiconductor wet etchant may be applied to back and sidesurfaces of the first interconnection forming structure 184 or thesecond interconnection forming structure 188 along lines F2 and F3 asshown in FIG. 5 or 6. The semiconductor wet etchant may be used in asingle-type semiconductor wet etching equipment. The semiconductor wetetching equipment may rotate the first interconnection structure 184 orthe second interconnection structure 188 at 1500 rpm/60 (sec.) whilespraying the semiconductor wet etchant.

The semiconductor wet etching equipment may form a protection layercovering a main surface of the first interconnection forming structure184 or the second interconnection forming structure 188 along a line F1of FIG. 5 or 6. The protection layer may be an inert gas, a nitrogen gasor a deionized water. The protection layer functions such that thesemiconductor wet etchant is not in contact with the second metal layer150, which is disposed on the main surface of the first interconnectionforming structure 184 or the second interconnection forming structure188 of FIGS. 3 and 4. When the first and second interconnection formingstructures 184 and 188 have the mask pattern 170, the protection layermay not be formed on the main surfaces of the first and secondinterconnection forming structures 184 and 188. This is because the maskpattern 170 covers the second metal layer 150, which is disposed on themain surface of the first or second interconnection forming structure184 or 188.

The semiconductor wet etching equipment may spray the semiconductor wetetchant on the back surface of the first or second interconnectionforming structure 184 or 188 along the line F2 of FIG. 5 or 6. Moreover,the semiconductor wet etching equipment may spray the semiconductor wetetchant along the line F3 of FIG. 5 or 6 to occupy an area from the sidesurface to the main surface, or from the main surface to the sidesurface of the first or second interconnection forming structure 184 or188 by a predetermined width W2. Accordingly, the semiconductor wetetchant sprayed along the line F3 contacts the main and side surfaces ofthe first or second interconnection forming structure 184 or 188. Thesemiconductor wet etching equipment may simultaneously or sequentiallyspray the semiconductor wet etchant along the lines F2 and F3. Afterthat, the first or second interconnection forming structure 184 or 188is rinsed with the deionized water while rotating at 1500 rpm/25 (sec.)in the single-type semiconductor wet etching equipment, and then driedusing nitrogen gas while rotating at 2500 rpm/30 (sec.).

FIG. 7 is a cross-sectional view showing a first interconnectionstructure after applying a semiconductor wet etchant to a firstinterconnection forming structure of FIG. 3. FIG. 8 is a cross-sectionalview showing a second interconnection structure after applying asemiconductor wet etchant to a second interconnection forming structureof FIG. 4.

Referring to FIGS. 3, 4, 7 and 8, in step S90 of FIG. 1, thesemiconductor wet etchant and the protection layer may be applied to thethird insulating layer 160, the second metal layer residues 155, thefirst metal layer 140, and the first and second insulating layers 110and 120 until the semiconductor substrates 100 of FIGS. 3 and 4 areexposed. To this end, the semiconductor wet etchant may remove the firstand second insulating layers 110 and 120 and the first metal layer 140which correspond to an area extending by the predetermined width W2toward the main surface from the side surface of the firstinterconnection forming structure 184 of FIG. 3. The semiconductor wetetchant may remove the third insulating layer 160, the first metal layer140 and the first and second insulating layers 110 and 120 whichcorrespond to an area extending by a predetermined width W2 toward themain surface from the side surface of the second interconnection formingstructure 188 of FIG. 4. As a result, the semiconductor wet etchant mayremove the second metal layer residues 155 from the semiconductorsubstrate 100 of FIG. 3 or 4 through the first, second and thirdinsulating layers 110, 120 and 160, and the first metal layer 140.

While the semiconductor wet etchant is applied to the first to thirdinsulating layers 110, 120 and 160, and the first metal layer 140 ofFIGS. 3 and 4, the protection layer and the mask pattern 170 protect thesecond metal layer 150, which is disposed in a device-forming region Dof the semiconductor substrate 100, from the semiconductor wet etchantas shown in FIG. 7. The protection layer may also protect the secondmetal layer 150, which is also disposed in the device-forming region Dof the semiconductor substrate 100 together with the mask pattern 170and the third insulating layer 160, from the semiconductor wet etchantas shown in FIG. 8. Thus, the semiconductor wet etchant may form a firstinterconnection structure 194, which includes the semiconductorsubstrate 100, the first and second insulating patterns 115 and 125, thefirst metal pattern 145 and the second metal layer 150, as shown in FIG.7. Further, the semiconductor wet etchant may form a secondinterconnection structure 198, which includes the semiconductorsubstrate 100, the first and second insulating patterns 115 and 125, thefirst metal pattern 145, the second metal layer 150 and the thirdinsulating pattern 165, as shown in FIG. 8.

After forming the first and second interconnection structures 194 and198, in step S100 of FIG. 1, the mask pattern 170 is removed from thefirst or second interconnection structure 194 or 198. The mask pattern170 may be removed using a semiconductor wet etching process having adifferent etch selectivity from the semiconductor substrate 100, thefirst to third insulating patterns 115, 125 and 165, and the first andsecond metal patterns 145 and 150. Subsequently, a chemical mechanicalpolishing technique may be applied to the first and secondinterconnection structures 194 and 198, thereby completing asemiconductor damascene process.

The present invention is not limited to a semiconductor wet etchingprocess which is performed using semiconductor wet etching equipment.The present invention may be applied to a conventional semiconductor wetetching process which is performed using a different type ofsemiconductor wet etching equipment well known to those skilled in theart, other than a single-type one. To this end, the different type ofsemiconductor wet etching equipment may be a semiconductor cleaningequipment. Also, the present invention is not limited to thesemiconductor wet etching process which is performed using a maskpattern. The present invention may be applied to the semiconductor wetetching process performed only using a protection layer other than themask pattern.

As described above, the present invention is related to a semiconductorwet etchant and a method of forming an interconnection structure usingthe same. The semiconductor wet etchant may provide an interconnectionstructure having a copper concentration of 0.6E10 (atoms/cm²) by easilyremoving insulating layers and metal layers disposed in a peripheralregion of a semiconductor substrate. Accordingly, the semiconductor wetetchant may reduce metal contamination which can occur in the peripheralregion of the semiconductor substrate, and thus may stabilize a processenvironment in the subsequent semiconductor manufacturing process for aninterconnection structure.

Exemplary embodiments of the present invention have been disclosedherein and, although specific terms are employed, they are used and areto be interpreted in a generic and descriptive sense only and not forpurpose of limitation. Accordingly, it will be understood by those ofordinary skill in the art that various changes in form and details maybe made without departing from the spirit and scope of the presentinvention as set forth in the following claims.

1. A method of forming a semiconductor device, comprising: providing asemiconductor substrate; and treating the semiconductor substrate usinga chemical solution comprising deionized water, and a fluorine-basedcompound, an oxidizer and an inorganic salt mixed in the deionizedwater, wherein a concentration of the fluorine-based compound is 0.25 to10.0 wt % based on a total weight of the chemical solution, aconcentration of the oxidizer is 0.45 to 3.6 wt % based on a totalweight of the chemical solution, and a concentration of the inorganicsalt is 1.0 to 5.0 wt % based on a total weight of the chemicalsolution, and wherein the inorganic salt comprises at least one of anammonium ion (NH₄ ⁺) and a chlorine ion (Cl⁻).
 2. The method accordingto claim 1, wherein the fluorine-based compound comprises at least oneof fluorine hydride (HF), ammonium fluoride (NH₄F), ammonium bifluoride(NH₄HF₂), tetra-methyl ammonium fluoride (TMAF; (CH₃)₄NF) andtetra-butyl ammonium fluoride (TBMA; (CH₃CH₂CH₂CH₂)₄NF).
 3. The methodaccording to claim 1, wherein the oxidizer comprises at least one ofhydrogen peroxide (H₂O₂), nitric acid (HNO₃), sulphuric acid (H₂SO₄),ammonium nitrate (NH₄NO₃), ammonium iodate (NH₄IO₃) and ammoniumdisulfate ((NH₄)₂S₂O₅).
 4. The method according to claim 1, wherein theinorganic salt comprises the ammonium ion (NH₄ ⁺), and wherein anon-metal atom is bonded to the ammonium ion (NH₄ ⁺).
 5. The methodaccording to claim 4, wherein the non-metal atom is selected from thegroup consisting of chlorine (Cl), bromine (Br), Iodine (I) and carbonicacid (CO₃).
 6. The method according to claim 1, wherein the inorganicsalt comprises the chlorine ion (Cl⁻), and wherein a metal atom isbonded to the chlorine ion (Cl⁻).
 7. The method according to claim 6,wherein the metal atom is selected from the group consisting of sodium(Na), kalium (K), calcium (Ca) and cesium (Cs).
 8. The method accordingto claim 1, wherein the inorganic salt comprises both the ammonium ion(NH₄ ⁺) and the chlorine ion (Cr), wherein a non-metal atom is bonded tothe ammonium ion (NH₄ ⁺), and a metal atom is bonded to the chlorine ion(Cl⁻).
 9. The method according to claim 8, wherein the non-metal atom isselected from the group consisting of chlorine (Cl), bromine (Br),Iodine (I) and carbonic acid (CO₃), and the metal atom is selected fromthe group consisting of sodium (Na), kalium (K), calcium (Ca) and cesium(Cs).
 10. The method according to claim 1, further comprising anon-ionic surfactant mixed in the deionized water, wherein thesurfactant is a co-polymer of ethylene and propylene.
 11. The methodaccording to claim 1, wherein the semiconductor substrate includes adevice-forming region and a device-excluding region surrounding thedevice-forming region on one surface thereof.
 12. The method accordingto claim 11, the chemical solution is applied to the device-excludingregion.
 13. The method according to claim 11, wherein the semiconductorsubstrate includes an insulating layer, a first metal layer and a secondmetal layer which are sequentially stacked, wherein the insulating layerand the first metal layer extend from the device-forming region towardthe device-excluding region, and wherein the second metal layer is onthe device-forming region.
 14. The method according to claim 13, whereinthe chemical solution is applied to the insulating layer and the firstmetal layer formed around the device-forming region.
 15. The methodaccording to claim 11, wherein the semiconductor substrate includes aninsulating layer, a first metal layer and a second metal layer which aresequentially stacked, wherein the insulating layer and the first metallayer cover the one surface and the other surface around the onesurface, and wherein the second metal layer covers the device-formingregion.
 16. The method according to claim 15, wherein the treating ofthe semiconductor substrate using the chemical solution includesspraying the chemical solution on the insulating layer and the firstmetal layer covering the other surface to etch the insulating layer andthe first metal layer on the other surface and expose the semiconductorsubstrate on the other surface.
 17. A method of forming a semiconductordevice, comprising: preparing a semiconductor substrate including a mainsurface, a back surface opposite the main surface and a side surfaceconnecting the main and back surfaces, forming a material layer on thesemiconductor substrate, the material layer covering the main surface,the side surface and the back surface; and spraying a chemical solutionon the material layer, the chemical solution being applied on at leastthe side surface and the back surface, and the chemical solutioncomprising deionized water, and a fluorine-based compound, an oxidizerand an inorganic salt mixed in the deionized water, wherein aconcentration of the fluorine-based compound is 0.25 to 10.0 wt % basedon a total weight of the chemical solution, a concentration of theoxidizer is 0.45 to 3.6 wt % based on a total weight of the chemicalsolution, and a concentration of the inorganic salt is 1.0 to 5.0 wt %based on a total weight of the chemical solution, and wherein theinorganic salt comprises at least one of an ammonium ion (NH₄ ⁺) and achlorine ion (Cl⁻).
 18. The method according to claim 17, wherein thematerial layer includes a lower layer and an upper layer, and the upperlayer is on a center region of the main surface, and the lower layer isexposed from the upper layer.
 19. The method according to claim 18,wherein the upper layer includes conductive material, and the lowerlayer includes conductive and insulating materials.
 20. The methodaccording to claim 18, wherein the spraying of the chemical solution onthe material layer includes etching the lower layer on the remainingregion surrounding the central region in the main surface, the sidesurface and the back surface.